Fpga Government Bids & RFPs
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Dept Of Defense- Dept Of The Navy- Onr- Onr Nrl- Naval Research Laboratory
Fpga
XILINX Zynq Ultra Scale - SEE ATTACHED DREVISED BID SCHEDULE AND COMBINED SYNOPSIS SOLICITATION This is Xilinx s Brand Name Only RFQ. Quotes for Equivalent Items will not be considered. A
bid schedule of supplies or services xilinx zynq ultrascale zu29dr 1 speed rfsoc based system on module with 16 channels of rfadcs @2. 5gsps and 16 channels of rfdacs @10gsps, programmable rf pll, data uart, spi, pcie, usb3. 0, sata3. 1, display port, gigabit ethernet, 64bit 8gb pl ddr4, 64bit 8gb ps ddr4 with ecc, 32gb emmc flash, jtag header, power regulation, linux bsp and user manual. form factor less than or equal to 100mm x 90mm. 4 weeks or less lead time. xilinx zynq ultrascale **** kit with installed som, breakout connectors, linux bsp. 4 weeks or less lead time. xilinx zynq ultrascale **** email and phone support
Bid Close Date:
Energy, Department Of- Energy, Department Of- Brookhaven Natl Lab - Doe Contractor
Xilinx FPGA for Gen- 2 Cell Controller, Must be an Authorized Distributor - Can you kindly quote the below into my name with the current date and lead time. Please offer BSA any discounts available for your Best Price. Items to be quoted
xczu15eg ****: **** ea
Bid Close Date:
Energy, Department Of- Energy, Department Of- Slac Natl Accel Lab - Doe Contractor
Chassis - SLAC National Accelerator Laboratory is operated by Stanford University for the Department of Energy. As a management and operating contractor, subcontracts awarded by the Laboratory are not Federal procurements, and are not directly subject to th
General Science and Technology R& D Services qty: 1 product description: chassis, rack mountable, 3u length: 77 cm, 2 power supplies, 6 fans, and 8 blank fems qty: 2 product description: 8 analog outputs @2gs s. 750 mhz badnwidth, 1 vpp or 330 mhz bandwidth, 5vpp 2 analog inputs @2gs s, 750 mhz bandwidth, 8 digital outputs 3. qty: 1 product description: 2 analog outputs, 2 analog inputs 2 analog outputs, 16 bits resolution: frequency range: 50 mhz 10. 5 ghz, multiplexed tone badnwidth: 300mhz, instantatneous bandwidth: 800 mhz, software upgradeable to 8 analog outputs 2 analog inputs, **** mhz bandwidth, 12 bits resolution: rnage: 1. 8 ghz 10. 5 ghz, 8 digital outputs, 16 cores fpga based pulse processor
Bid Close Date:
Energy, Department Of- Energy, Department Of- Slac Natl Accel Lab - Doe Contractor
Chassis - SLAC National Accelerator Laboratory is operated by Stanford University for the Department of Energy. As a management and operating contractor, subcontracts awarded by the Laboratory are not Federal procurements, and are not directly subject to th
General Science and Technology R& D Services qty: 1 product description: chassis, rack mountable, 3u length: 77 cm, 2 power supplies, 6 fans, and 8 blank fems qty: 2 product description: 8 analog outputs @2gs s. 750 mhz badnwidth, 1 vpp or 330 mhz bandwidth, 5vpp 2 analog inputs @2gs s, 750 mhz bandwidth, 8 digital outputs 3. qty: 1 product description: 2 analog outputs, 2 analog inputs 2 analog outputs, 16 bits resolution: frequency range: 50 mhz 10. 5 ghz, multiplexed tone badnwidth: 300mhz, instantatneous bandwidth: 800 mhz, software upgradeable to 8 analog outputs 2 analog inputs, **** mhz bandwidth, 12 bits resolution: rnage: 1. 8 ghz 10. 5 ghz, 8 digital outputs, 16 cores fpga based pulse processor
Bid Close Date:
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